Subject: [Fwd: rfc1407 DS3 MIB questions]

From: Eric Bomarsi <[email-masked]>
Date: Tue, 16 Dec 1997 07:54:30 -0500

Subject: rfc1407 DS3 MIB questions
From: Eric Bomarsi <[email-masked]>
To: [email-masked]
Cc: ebomarsi
Date: Mon, 15 Dec 1997 19:26:13 -0500

A couple of questions on rfc1407 DS3 MIB. (Pardon my DS3 ignorance).

1) Many devices have a counter for F and M bit errors in addition
   to error events (LCVs, PCVs, and CCVs). How are F/M bit errors
   accounted for in the ds3 mib?

2) UAS Description says:

   "With respect to the DS3 error counts, all counters are incremented
    while the DS3 interface is deemed available.  While the
    interface is deemed unavailable, the only count that is
    incremented is UASs."

   What exactly are the "error counts"? Are they the code violations
   (LCVs, PCVs, CCVs) and/or the performance parameters? 
   Most of the performance parameters (except UASs) explicitly state
that
   they are not to be incremented when the interface is unavailable.
   These include PESs, PSESs, CESs, CSESs. However the remaining two
   (LESs and SEFSs) do not state anything, so should they increment or
   not?

Thanks in advance,
/Eric Bomarsi

---

From: Eric Bomarsi <[email-masked]>
Date: Mon, 22 Dec 1997 14:15:35 -0500

>    accounted for in the ds3 mib?

Someone suggested (with uncertainty) that F and M-bit errors are 
not counted in the MIB, however these will result in 'Out Of Frame'
(OOF) error events which cause errored seconds.

Can anyone confirm this?

Thanks in advance.
/Eric Bomarsi